ULTRA300

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Description

 

Device ULTRA300
Capacity of modules
Register 273 408
LUT-4 290 496
Carry 68 352
Embedded RAM
Core RAM Blocks (48K-bit) 448
Core RAM Bits (K = 1024) 21 504
Core Register File Blocks (32 x 18-bit) 1 436
Core Register File Bits 807 K
Embedded DSP 896
Clocks 50
DAC 4
ADC 4
Embedded Serial Link
HSSL 12,5 Gbps, SERDES TX/RX

SpaceWire with codec 400Mbps

16
1
I/Os
I/O Complex Banks 10 (34 I/Os per bank)
I/O Direct Banks  6 (24 I/Os per bank) + 1 (16 I/Os per bank)
I/O Service Bank 1   (47 I/Os)
User I/Os 547
Available Packages
  BGA-484 limited peripherals
  BGA-1152

Radiation Tolerance

  • Radiation hardening by design in configuration memories and registers.
  • SEU immune up to LET > 60MeV.cm2/mg.
  • Total ionizing dose > 50Krads (Si).
  • Embedded EDAC for user memory mitigation.
  • Embedded configuration memory scrubbing.
  • Fast automatic memory configuration repair.
  • Embedded bitstream integrity check (CMIC).

Main Features

  • 28 nm STMFDSOI process technology.
  • 12-bit ADC, 13-bit DAC
  • 4-Input Look-up tables.
  • LUT expender to support up to 16 bits boolean functions.
  • High performance carry chains.
  • Advanced interconnect network to support random logic and coarse grain block functions.
  • DSP Blocks for complex arithmetic operations.
  • User memories with variable width and depth.
  • Configuration modes: JTAG, Parallel 16 bits, Master Serial SPI, SpaceWire, Flash and UART.
  • Integrated Space Wire interface available for user applications.
  • Dedicated lowskew distribution network for clock, reset and load enable signals.
  • On-chip thermal sensor.

Input / Output Features

  • Multi voltage I/O support from 1.2V to 3.3V
  • Cold sparing support.
  • Programmable output drive to support multiple industry standards.
  • Embedded logic to support DDR2, DDR3 and DDR4.
  • Up to 1.6 Gbps maximum I/O support for SSTL, HSTL and POD standards.
  • LVDS compatible mode.
  • All pins support 2000V of ESD-HBM.
  • Embedded logic to support Space Wire Data Strobe encoding.
  • Programmable delay lines on complex I/O pins.
  • Programmable resistive termination on complex I/O pins.