SoCs, FPGA, eFPGA

NanoXplore is a privately owned fabless company based in France. The company offers a comprehensive portfolio of SoCs and FPGA devices for aerospace, defense and industrial markets. Products include a leading radiation hardened FPGA portfolio. 

Corporate profile

NanoXplore is a privately owned fabless company based in France. The company offers a comprehensive portfolio of SoCs and FPGA devices for aerospace, defense and industrial markets, including state of the art rad hard FPGA based technology

Corporate profile

NanoXplore is a privately owned fabless company based in France. The company was created in 2010 by three veterans of semiconductor industry with long experience in the design, test and debugging of FPGA.

The founders of NanoXplore were amongst the pioneers of custom FPGA based emulation systems and IP macros for embedded FPGA cores. In 2000, they developed the first range of IP macros to provide programmable logic cores for System on Chip (SoC) designs. In 2006 they developed a new family of FPGA devices with 750K four-input LUTs implemented in a 65nm technology.

Based on his team's long standing FPGA development track record, NanoXplore has designed a leading radiation hardened FPGA portolio for aerospace, defense and industrial market.

Management


Olivier Lepape - Co-Founder & CEO

Olivier Lepape is a co-founder of NanoXplore and CEO. Before starting NanoXplore, he was co-founder and Vice President of Hardware Engineering of AboundLogic where he developed the first 750k LUTs FPGA in 65nm in 2009. Before AboundLogic, Olivier was co-founder and Vice President of Engineering of Meta Systems, later acquired by Mentor Graphics where he was in charge of all hardware and software development for ASIC emulator products. Before Meta Systems, Olivier was at Dune Technology, also a logic emulation company where he developed the first proprietary FPGA architecture based on hierarchical switching networks, as well as place & route algorithms. Olivier started his career at Matra Data Systems, then moved to ES2 (a European ASIC foundry) where he was a custom IC designer. Olivier graduated from Supelec and holds an MSEE from Stanford University (CA). He is co-inventor of 22 patents focused on emulation systems and reprogrammable logic.

Edouard Lepape - Head of Business Development and CFO

Edouard Lepape is Head of Business Development and CFO at NanoXplore. Before joining NanoXplore, Edouard worked 5 years in investment banking in corporate finance advisory at Barclays, JP Morgan and Citi. He worked on various corporate finance transactions including multi billions euros M&A and corporate financing (DCM, ECM, LCM) transactions. Before that Edouard worked at KPMG in Accounting. Edouard graduated from the Business School ESSEC.

Damien Dupuis - Software Team Leader

Damien Dupuis is the Software Team leader at NanoXplore.  He has 15 years of experience in EDA software C++ development. For the past 10 years, he has worked in the FPGA domain as a developper specialized in graphical interface creation using Qt and Python wrapper over C++. Before working in the FPGA domain, he was a research engineer at the LIP6 institute where he was involved in the development of the academic VLSI set of tools Coriolis, for mixed analog and digital ASIC design. Damien graduated his PhD degree in electronics from the University Pierre et Marie Curie in 2009.

Remy Escassut - Head of Software Engineering

Rémy Escassut is Head of Software Engineering at NanoXplore. He is an industry veteran with 25 years of experience in EDA software. Rémy is inventor of the powerful concept of generic collections which is the base of all its works. He is a specialist of high speed graphical interface and compliant GUIs. Before starting NanoXplore, he was engineer of AboundLogic (formerly M2000) in charge of the conception, the development, the new technologies adaptations and the support of the proprietary physical design tool. Before AboundLogic he was engineer of SILVACO, where he evaluate the OpenAccess database and develop an extendible data structure. He was, at the end, in charge to prototype a standard cell placer and router based on this proprietary framework. Before Silvaco he was engineer of BULL where he was in charge of the development (in lisp and C++) of the proprietary floorplanning and routing tool. He collaborates with the Lip6 to provide them the hierarchical data structure (Hurricane) that is the base over which the Lip6 Tsunami package is founded. Rémy graduated from the University of Montpellier in 1988.

Jean Barbier- Co-Founder & CTO

Jean Barbier is a co-founder of NanoXplore and CTO.
Before starting NanoXplore, he was co-founder of AboundLogic/M2000 where he worked on the first 750k LUTs FPGA in 65nm in 2009. Before AboundLogic, Jean was co-founder of Meta Systems, later acquired by Mentor Graphics where he was in charge of system & boards hardware and early software development for ASIC emulator products. Before Meta Systems, Jean was at Dune Technology, also a logic emulation company where he co-developed the first proprietary FPGA architecture based on hierarchical switching networks, and GUI for Mapping. Jean started his career at MBC-Alcyane, later part of Matra Data Systems developping micro then mini computers. Jean graduated from University Pierre et Marie Curie - Paris VI in 1980. He is co-inventor of 18 patents focused on emulation systems and reprogrammable logic. 

Philippe Piquet - Co-Founder and Head of Hardware Engineering

Philippe Piquet is co-founder of NanoXplore and Head of Hardware Engineering. Before starting NanoXplore, he was at AboundLogic where he was in charge of embedded FPGA Core development using different technology nodes, ranging from 130nm to 45nm. He headed the custom design group in charge of a 750K LUTs FPGA core. Before AboundLogic, Philippe worked at GlobespanVirata where he was in charge of custom SRAM design and backend for a 10 processor chip dedicated to the telecom market. Before that, Philippe was a full custom IC designer at Temic. Philippe started his career at Sicon (Linköping, Sweden) and then moved to Carlstedt Elektronik (Gothenburg, Sweden) where he worked on an advanced ALU and other complex logic modules. Philippe graduated from INSAT and from the University of Toulouse in 1989. Philippe is co-inventor of various patents focused on reprogrammable logic structures.

Joël Le Mauff - Head of Marketing and Sales

Joël Le Mauff is head of marketing and sales. He worked as Business Development and sales manager at Alter Technology. Before that he was a self-employed consultant in the aeronautics, military & space sector. He has extensive experience in the field of FPGA since he worked 9 years at Xilinx as Business Development manager. He also worked at Atmel as tactical marketing and customer manager. Joël graduated from Conservatoire National d’Arts et Métiers (CNAM) in 1986.

Partners

NanoXplore is strongly supported by European institutions and public agencies

Corporate responsability

As a company, we are committed to being beyond reproach to all our partners. But because we are aware of the challenges of today's world, we also want to be just as exemplary to society as a whole. We promote values in which we firmly believe as innovation that must be collaborative to be effective, thus creating an innovative dynamic that benefits everyone. We also want to be responsible towards our employees or partners, but also towards the environment that we are committed to preserve. Finally, ethics is at the heart of our concerns, from the transparency we impose on ourselves towards all our partners to the fight against corruption and influence peddling, we do everything we can to adopt socially responsible behaviour. This is why we have made commitments in terms of the environment, ethics and respect for our employees and partners.

Governance

NanoXplore's management defines the CSR policy in a charter ratified by all employees. We ensure that it is applicable in the company's various premises by providing our employees with the necessary means to apply the directives set. Management has appointed a CSR Manager who ensures that commitments are met and provides feedback on employees' ideas and comments in a continuous improvement process. Finally, the Management is committed to complete financial and accounting transparency and has its accounts certified by an external body.

Community

A commitment to our employees

Our HR policy aims to promote equal opportunities as well as professional and social diversity. We promise all our employees a safe, pleasant and environmentally responsible workplace in which they can develop their skills and develop their careers in order to achieve both their professional and personal goals.

Collaboration for innovation

At NanoXplore we promote collaborative projects because we are firmly convinced that innovation and progress can only come from a combination of experiences and horizons. That is why we work from the beginning to the end of projects with our suppliers, subcontractors and customers so that everyone's know-how leads everyone to a real technological achievement. We also partner with university research laboratories to benefit from the latest technological advances but also to make our contribution. All the partnerships we develop are destined to last over time since only a real relationship of trust can achieve the best results. Finally, we ensure that all partners with whom we contract respect the values in which we believe.

Environment

We are committed to an eco-responsible approach that we want to develop as we grow. We therefore ensure that all our employees have the opportunity to travel to their workplace by public transport. Our employees are made aware of waste sorting and eco-citizen actions in their daily lives. We are also committed to recycling all our computer equipment. For the lighting of our premises, we have chosen low-energy LED bulbs triggered by a motion detection device to limit energy waste. Our head office is now located in Sèvres, a city that actively promotes the sorting and recycling of waste and the protection of space.

Products

Software tools

NanoXplore provides a design suite that supports all NanoXplore FPGA families. NanoXplore design suite runs on Linux 64 bits operating systems. The supported distributions are RedHat Enterprise 6 & 7, Ubuntu LTS 14.04, 16.04 & 18.04 and Debian 9.

RHBD FPGA, SoCs, eFPGA

NanoXplore has developed Radiation-Hardened By Design SRAM-based FPGA devices for use into systems operating in harsh environments, such as Spaceborne and Airbone applications, as well as Military and High-Energy Physics subsystems.

NXmap

NXmap is the main tool of NanoXplore design suite. It allows user to perform the design flow to program a FPGA including, synthesis, place, route, static timing analysis and bitstream generation. NXmap consists in a set of C++ libraries that can be controlled either through a graphic user interface or through a Python wrapper for scripting.

NXcore

NXcore is a graphical user interface that presents all IP cores available for NanoXplore FGPA families. In addition to presenting each IP core and linking to the provider company, NXcore allows user to graphically define the parameters of some IP cores and generate the preconfigured and encrypted VHDL code that can be used as input of NXmap.

NXscope

NXscope is an embedded logic analyzer. It allows to sample a collection of internal data synchronously with a user’s clock (rising edge sensitive) and analyze the sampled results in a waveform viewer. NXscope is a NanoXplore IP Core. It’s generated by using the NXcore generator. The capture process is controlled by JTAG via the ANGIE USB-JTAG adapter with commands supported by NXbase2 software or NXboard GUI. The results can be displayed and analyzed either with :

  • ModelSim wafeform viewer (using a simple testbench to read the .txt file generated by NXcore generator and display the waveforms).
  • GTKWave (free waveform display tool)

NXbase2 & NXboard

NXbase2 is a command-line tool that can interact with evaluation kit boards for NanoXplore’s chips. It provides a way to upload bitstream files into the chip and is able to control some of the hardware features of the related evaluation kits. The communication between computer and evaluation kit board is done by JTAG via the ANGIE USB-JTAG adapter provided with the evaluation kit board. NXboard is a graphical user interface, using NXbase2, that allows easy interaction with the evaluation kit boards.

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Rad-hard FPGA & SoCs

NanoXplore has developed Radiation-Hardened By Design SRAM-based FPGA devices for harsh environments applications.
By nature, SRAM-based FPGAs are volatile. NanoXplore has developed a dedicated architecture based on hardening techniques such as

  • DICE (Dual Interlocked storage CEll) memory latch. DICE architecture has been used for Configuration Memory Cells and Internal registers (DFFs)
  • EDAC for BRAM blocks
  • TMR (Triple Module Redundancy) for all other blocks

Based on this hardening approach, our rad-hard SRAM FPGA are much more reliable than traditional SRAM FPGA in harsh environment.
To even furhter improve the reliability of our FPGA, NanoXplore has developped an advanced Configuration Memory Integrity Check ("CMIC"). CMIC is an internal scrubber controller based on a Finite State Machine with its own hardened memory block to store CRC signatures. The CMIC will constantly verify the integrity of the bitstream and any potnential single errors will be detected and corrected.

NG-Medium

NG-Medium is a low-end RHBD FPGA device. Its P/N is NX1H35AS. Hereafter a short view of the NG-Medium:

and what are NG-Medium available resources:

  • Logic: 34272 LUT4 + 32256 DFFs + 8064 CY chains
  • Memories: 56 BRAM Blocks of 48kb (= 2688kb), going down 36kb with EDAC activated + 168 Register Files of 168*64bits also protected by EDAC.
  • DSP: The NG-Medium has 112 DSP blocks which can be cascaded.

As well as

  • SpaceWire: The NG-Medium has 1 SpW CODEC and 16 PHYs
  • DDR2: The NG-Medium has 16 DDR2 PHYs

In term of clocking, the NG-Medium has 24 clock domains splited within 4 clock generators (CKG) including their own PPL.

The NG-Medium is packaged in

  • Ceramic QFP352 + LGA625 + CGA625
  • Organic PBGA625

NG-Large

NG-Large is a mid-end RHBD FPGA device. Its P/N is NX1H140TSP. Hereafter a short view of the NG-Large:

and what are NG-Large available resources:

  • Logic: 137088 LUT4 + 129024 DFFs + 32256 CY chains
  • Memories: 192 BRAM blocks of 48kb (= 9216kb), going down 36kb with EDAC activated + 672 Register Files of 168*64bits also protected by EDAC
  • DSP: The NG-Large has 384 DSP blocks which can be cascaded

As well as

  • SpaceWire: The NG-Large has 1 SpW CODEC and 20 PHYs
  • DDR2: The NG-Large has 20 DDR2 PHYs

2 majors additional resources have been added into the NG-Large:

  • 24 SERDES operating from 0,70 to 6,25Gbps allowing to comply to many protocols such as
    • WizardLink
    • JESD204B, ESIstream
    • Serial Rapid I/O (SRIO)
    • SpaceFibre (SpFi)
  • Hard IP Processor type ARM Cortex-R5

In term of clocking, the NG-Large has 32 clock domains splited within 4 clock generators (CKG) including their own PPL.

The NG-Large is packaged in

  • Ceramic LGA1752 + CGA1752
  • Organic Fine pitch Flip-chip 1752 balls (FF1752)

NG-Ultra

NG-Ultra is a high-end RHBD FPGA device. Its P/N is NX2H540TSC.

Hereafter what are NG-Ultra available resources:

  • Logic: 536928 LUT4 + 505344 DFFs + 126336 CY chains
  • Memories: 672 BRAM blocks of 48kb (= 32256kb), going down 36kb with EDAC activated
  • DSP: The NG-Ultra has 1344 DSP blocks which can be cascaded

As well as

  • SpaceWire: The NG-Ultra has 1 SpW CODEC and 20 PHYs
  • DDR2: The NG-Ultra has 20 DDR2 PHYs

2 major additional resources have been added into the NG-Large:

  • 32 SERDES operating up 12,50Gbps allowing to comply to many protocols
  • A complete System-On-Chip named DALHIA architecture with a Quad-core ARM Cortex-R52

The NG-Ultra is packaged in

  • Ceramic LGA1752 + CGA1752
  • Organic Fine pitch Flip-chip 1752 balls (FF1752)

eFPGA

NX-eFPGA is a family of SRAM based programmable logic blocks implemented with 4 inputs LUT and DFF fabric. Build on state-of-the-art, high routing flexibility, high density, low power programmable interconnect network, NX-eFPGA offers an innovative and unparalleled solution to introduce hardware flexibility in future ASIC and SOC in a cost effective way. On advanced node, the area expansion is very limited and in many pad limited applications, die area can well be constant.

NX-eFPGA blocks are programmed with our in house mapping software (NXmap) performing all required steps to transform a synthesizable RTL description into a bit stream downloadable in the NX-eFPGA through various hardware interfaces. The mapping process is built on advanced proprietary algorithms optimized for the architecture and capable of handling complex routing structures as well as LUT utilization greater than 90%.

Flexibility is a constant concern for all logic products. Traditionally, MCU and RAM provided system level flexibility. Now, NanoXplore can provide the missing link to bring this essential capability directly in your logic functions. NanoXplore breaks the technical and economic barriers to adding hardware flexibility to your SoC or ASSP.

Business Model

Our eFPGA IP is available in the form of standard silicon proven hard macros easy to integrate on to SoCs. We provide support and all required environment that simplifies the process of integration and productization.

Our standard eFPGA IP is available on a per use basis with upfront license fee without royalties. The license fee also gives access to all our software environment NanoXmap. NanoXmap provides a complete tool suite to map your Verilog or VHDL application to our eFPGA cores.

We also offer a very flexible approach for specific customization requests to our existing eFPGA IP. We can offer bigger logic capacity block, embed user specific functions within the fabric and port our existing technology to any foundry and node. Our customization approach aims at guarantying product success and required functions in a defined timeframe.

NanoXplore has developed a scalable eFPGA architecture and an efficient implementation methodology based on proprietary layout generation and verification tools to realize higher LUT capacity in order to address specific user demands. Through this custom program, NanoXplore can deliver up to 750K LUT fabrics with embedded DP-RAM, DSP or any user specific function, on the most advanced technology nodes such as 28nm.

Key Features

Our eFPGA IP includes the following standard features:

  • Real 4 inputs look-up table (LUT) technology to map combinatorial Boolean functions
  • SRAM based
  • Programmable flip-flop (DFF)
  • Fast carry chain structures (CYC)
  • Multiple clock (CLK)
  • Global signals (GS)
  • User I/O

We also offer optional features:

  • Single, dual or true dual port memory
  • Dual port register file
  • Multiplier and accumulator
  • Multiple clock zones

The NX-eFPGA can be programmed through various interfaces. The user can use any combination of them:

  • JTAG Interface
  • Serial SPI Interface
  • 16-bits Parallel Interface

JTAG and SPI interfaces are normally directly accessible through external IO buffers. The fabric JTAG tap controller can be chained with other on die tap controllers if necessary. The Parallel interface can be connected to one SOC internal bus.

Foundries

Our eFPGA technology is a silicon proven IP supporting mature technologies up to 28nm on leading foundries. Our IP is fully customizable to client’s needs.

Foundries available:

  • GlobalFoundries
  • TSMC
  • Samsung

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Support

If you have any questions, don’t hesitate to contact us at : support@nanoxplore.com

Documentation

All documentations associated to NanoXplore FPGA and NanoXplore design suite are available on the dedicated website : http://download.nanoxplore.com

User can register freely but only has Access to a subset on the documentations. Once a Software License Agreement has been signed, user gains Access to all documentations and software downloads.

Training

NanoXplore proposes NXmap training courses in order to allow users to exploit most of NXmap features.

This 3-day training is focused on both NanoXplore FPGA architecture and associated synthesis and implementation tools NXmap and NXPython.

Attendees pre-requisites are :

  • The attendees must have knowledge on VHDL language for both synthesis and simulation
  • Any experience on FPGA implementation will be useful

Hereafter what would be the agenda

  • NanoXplore technology overview
  • FPGA architecture overview
  • NXmap/NXpython overview
  • Basic script
  • NG-MEDIUM architecture
    • Clock management and distribution
    • RAM blocks
    • DSP blocks
    • I/O and SERDES
    • SpW support and IP core
  • NXpython advanced scripts
  • Timing constraints and timing analyzer
  • NXcore and NXscope
  • NG-Medium Configuration and NXbase2 software commands
  • Etc.

The NX training course will include many labs with for some of them the use of NX FPGA evaluation kit which will allow users to exercice NX tools and boards.

NX training courses are based of course of the latest NXmap version and associated tools (NXbase2, NXcore, NXboard, NXscope, etc.).

NX training courses could be customized according attendees FPGA experiences as well as users expectations.

Sales

Coming soon...

Careers

Joining us is integrating a dynamic, welcoming, and booming business. It is also part of strategic projects for prestigious customers

Our values and ethical commitments

They are expressed in the daily life of all our teams:

  • Innovation is in NanoXplore's DNA. It is the sign of the company's collaborative qualities, its ability to communicate and its will to constantly push the limits of knowledge. It creates an innovative dynamic, from the design stage to customer service, through the creation of products that open new paths, and allows us to stay ahead of time.
  • Responsibility: there is no innovation without team spirit, without challenges, without adventure, without a spirit of entrepreneurship. It is the driving force of a company which builds, above all, on trust in the individual and their talents. We also take responsibility for the impact of our activity on the environment. We are particularly attentive to ensuring the preservation of the environment.
  • The meaning of customers : NanoXplore promotes rules of transparency and ethics which allows us to build permanent relationships of trust. It includes vigilant against bribery and the trading of influence, the confidentiality and protection of knowledge, and ethical commitments in accounting and financial matters.

Working with NanoXplore

Joining us is integrating a dynamic, welcoming, and booming business. It is also part of strategic projects for prestigious clients.

As NanoXplore grows, all of our collaborators develop with it. We offer to talented men and women, who join us, the chance to discover not only the richness of our professions but also to live a professional experience within a rewarding and stimulating environment.

The recruitment process

When we receive an application, we do a first phone interview. This will allow us to measure the compatibility of your skills with our offer.

This step will be followed by an interview in our premises with the operational manager and the recruitment officer in order to get to know each other.

This interview will take place in several steps :

  • Understanding of your journey, technical knowledge, and your expectations
  • Presentation of our company
  • Appreciate your motivation and study your wishes for evolutions

In general, during this interview, we will evaluate your technical skills (a second purely technical interview may be organized thereafter).

After consultation with our teams, our decision will be communicated to you as soon as possible.

If your application is selected, our recruiting officer will return to you with a contractual proposal.

We will accompany you in your integration within our team and we will allow you to quickly master your new environment, to know your interlocutors to facilitate your integration steps.

If you want to apply, contact us at careers@nanoxplore.com

Job Openings

DESCRIPTION JOB
INGENIEUR DE TEST ET CARACTERISATION FPGA F/H
INGENIEUR CONCEPTION ASIC SENIOR F/H

In full expansion, we are constantly looking to strengthen its software and hardware development teams, in Paris or Montpellier. You wish to join NanoXplore and propose a spontaneous application, contact our HR department by email now: careers@nanoxplore.com

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3rd BRAVE FPGA Day

NX workshop - 26-27nov19, + 1:1 meeting - 28nov19
ESA/ESTEC Noordwijk, NL

NanoXplore offers competitive European rad-hard FPGAs enabling systems flexibility, high performance and miniaturization.

Following the last 2 successful ‘BRAVE FPGA Day’ workshop in ESA/ESTEC Noordwijk, NL, the 3rd BRAVE Day is coming.

1st BRAVE FPGA Day done in Sep-2017 was an introduction to NanoXplore FPGA solutions. 2nd BRAVE FPGA Day done in Nov-2018 focused on 1st experiences and incoming Flight Heritage.

The 3rd BRAVE FPGA Day will introduce

  • NX product marketing strategy, including our positioning on NEW SPACE market following the selection of NX within a Mega-Constellation of Satellites.
  • NXmap roadmap including incoming NXmap-v3 major update
  • NX product update on qualification, radiation performance including dedicated flow for New Space for:
    • NG-Medium
    • NG-Large
    • NG-Ultra
  • New rad-hard FPGA device ULTRA-150.
  • NX ecosystem update including
    • IP cores and Tools linked to NX products
    • End-users experience

Please register to the event, by sending an email to the NanoXplore contact joel.lemauff@nanoxplore.com including ESA and CNES contacts in copy.

January Facts Sheet

Happy New Year

Hello Madam, Sir, It is not too late. So, let’s me tell you Happy New Year 2020 to all of you. See you soon to address together your projet(s).

Last quarter has been very fruitful :

    • New NXmap-v2.9.6 has been released with several important features,
    • The brand new NXmap-v3 development is moving fast with anexpected beta status within coming days,
    • As presented at last BRAVE FPGA Days, 1st NG-Large prototypes have been evaluated successfully, allowing us to start the product industrialization,
    • The 1st-run NG-Ultra design is done. New NXmap-v2.9.6 has been released with several important features

    So, please find here attached the n°9 NX FACTS SHEET dated JAN20 which will reflect those statements. Feel free to come back to us for further details. As reported last time :

    • If you don’t want be part of our mailing list, please tell us by return and then, we will remove your email address.
    • On the opposite, if you want us to include one or several of your colleagues, tell us also and we will add them into the mailing list.

    SEFUW: SpacE FPGA Users Workshop, 5th Edition - UPDATE 02 March 2020: please be informed that SEFUW has been postponed. More information will be posted here in due course.

    17, 18 and 19 march 2020
    ESTEC Noordwijk The Netherlands

    The aim of the workshop is to share experiences and wishes among FPGA designers, FPGA vendors and research teams developing methodologies to address radiation mitigation techniques and reconfigurable systems. NANOXPLORE will present updates and will be available for questions.

    See you maybe at next SEFUW which will hold in ESA/ESTEC Noordwijk from 17 to 19th of Mar20. Do not forget to register till 28feb20 :

    https://indico.esa.int/event/328/registrations/176/

    • For more informations, please click here :

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